74 lines
1.6 KiB
Plaintext
74 lines
1.6 KiB
Plaintext
/**
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Takes many registers and only reads from ONE selected
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*/
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module registerDemultiplex (
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input clk, // clock
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input rst, // reset
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input selection[3], //which register? see node.luc for enumeration
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input acc[GNode.WORDLEN],
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input up[GNode.WORDLEN],
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input right[GNode.WORDLEN],
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input down[GNode.WORDLEN],
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input left[GNode.WORDLEN],
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input last[GNode.REGISTERADDRLEN], //CAREFULL! this is NOT a register! this is a address!
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input any[GNode.WORDLEN],
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output out[GNode.WORDLEN],
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output done, //TODO: implement this fully
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input read
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) {
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dff outb[GNode.WORDLEN](.clk(clk), .rst(rst), #INIT(0));
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always {
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//reading
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done = 0;
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if(read) {
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if(selection == 0) {
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outb.d = 0;
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done = 1;
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} else if(selection == 1) {
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outb.d = acc;
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done = 1;
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} else if(selection == 2) {
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outb.d = up;
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} else if(selection == 3) {
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outb.d = right;
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} else if(selection == 4) {
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outb.d = down;
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} else if(selection == 5) {
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outb.d = left;
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} else if(selection == 6) {
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//inner selection for last register
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case (last) {
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0: outb.d = 0; //NIL
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done = 1;
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1: outb.d = acc;
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2: outb.d = up;
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3: outb.d = right;
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4: outb.d = down;
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5: outb.d = left;
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7: outb.d = 0; //ANY - not implemented correctly!
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done = 1;
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}
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} else if(selection == 7) {
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outb.d = any;
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} else {
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outb.d = 0;
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done = 0;
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}
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} else {
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outb.d = 0;
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done = 0;
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}
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out = outb.q;
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}
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} |