/**


  Takes  many registers and only reads from ONE selected


*/
module registerDemultiplex (
    input clk,  // clock
    input rst,  // reset
    
    
    input selection[3], //which register? see node.luc for enumeration
    
    input acc[GNode.WORDLEN],
    input up[GNode.WORDLEN],
    input right[GNode.WORDLEN],
    input down[GNode.WORDLEN],
    input left[GNode.WORDLEN],
    input last[GNode.REGISTERADDRLEN],      //CAREFULL! this is NOT a register! this is a address!
    input any[GNode.WORDLEN],
    
    output out[GNode.WORDLEN],
    output done,  //TODO: implement this fully
    input read

  ) {
  
  dff outb[GNode.WORDLEN](.clk(clk), .rst(rst), #INIT(0));

  always {
    //reading
    done = 0;
    if(read) {
      if(selection == 0) {
        outb.d = 0;
        done = 1;
      } else if(selection == 1) {
        outb.d = acc;
        done = 1;
      } else if(selection == 2) {
        outb.d = up;
      } else if(selection == 3) {
        outb.d = right;
      } else if(selection == 4) {
        outb.d = down;
      } else if(selection == 5) {
        outb.d = left;
      } else if(selection == 6) {
        //inner selection for last register
        case (last) {
          0: outb.d = 0; //NIL
             done = 1;
          1: outb.d = acc;
          2: outb.d = up;
          3: outb.d = right;
          4: outb.d = down;
          5: outb.d = left;
          7: outb.d = 0; //ANY - not implemented correctly!
             done = 1;
        }
      } else if(selection == 7) {
        outb.d = any;
      } else {
        outb.d = 0;
        done = 0;
      }
    } else {
      outb.d = 0;
      done = 0;
    }
    out = outb.q;
  }
}