src added not working or anything
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work/
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19
README.md
19
README.md
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# TIS-100-FPGA
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# TIS-100 in Lucid for FPGA
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A try to implement TIS 100 on a FPGA
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I tried to implement [TIS-100](http://www.zachtronics.com/tis-100/) on a FPGA. I used the [Mojo-v3](https://alchitry.com/products/mojo-v3) from alchitry.
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You need a tool (i am going to create one soon) to send a savefile from you computer to the programed FPGA.
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Things currently not supported:
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* ANY register - would just act like the NIL register
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* graphical Output - nowhere to output too
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* Stackstorage Nodes - comimg later
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* debugging in any way
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* speed control (step, fast run)
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Keep in mind, that this is just a small Project to play around with a FPGA. I am pretty new to Lucid (the Language used) and i probably made every mistake - and bug - possible. So there is no warranty at all! But if you find something feel free to send me a message at `y.g.2 (at) gmx (dot) de`
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###### Licence
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This Project is Licenced under AGPLv3 a copy of the Licence should be alongside with the code.
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module mojo_top (
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input clk, // 50MHz clock
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input rst_n, // reset button (active low)
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output led [8], // 8 user controllable LEDs
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input cclk, // configuration clock, AVR ready when high
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output spi_miso, // AVR SPI MISO
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input spi_ss, // AVR SPI Slave Select
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input spi_mosi, // AVR SPI MOSI
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input spi_sck, // AVR SPI Clock
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output spi_channel [4], // AVR general purpose pins (used by default to select ADC channel)
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input avr_tx, // AVR TX (FPGA RX)
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output avr_rx, // AVR RX (FPGA TX)
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input avr_rx_busy // AVR RX buffer full
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) {
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sig rst; // reset signal
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.clk(clk) {
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// The reset conditioner is used to synchronize the reset signal to the FPGA
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// clock. This ensures the entire FPGA comes out of reset at the same time.
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reset_conditioner reset_cond;
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}
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always {
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reset_cond.in = ~rst_n; // input raw inverted reset signal
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rst = reset_cond.out; // conditioned reset
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led = 8h00; // turn LEDs off
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spi_miso = bz; // not using SPI
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spi_channel = bzzzz; // not using flags
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avr_rx = bz; // not using serial port
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}
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}
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@ -0,0 +1,110 @@
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global GNode {
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const ROWS = 14; //number of commands to hold
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const CMDLEN = 16; //number of bits a command is in size
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const WORDLEN = 11; //bits to store a number (-999 to 999)
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const REGISTERADDRLEN = 3; //bits to address a register
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struct cmd {
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cmd[4],
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arg_is_const, //1 = argument is a 11bit signed integer, 0 argument is a register number
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args[11] //11 bit number or at most 2 reigster (mov cmd)
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}
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}
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/**
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Register numbers:
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0 = NIL
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1 = ACC
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2 = UP
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3 = RIGHT
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4 = DOWN
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5 = LEFT
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6 = LAST
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7 = ANY
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Subclk:
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0 = Read cmd
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1 = interpret cmd
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2 = Mark input as read
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3 = try to read
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4 = mark output as read
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5 = write to output
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6 = increment pc and reset everything thats not needed anymore
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cycles are skiped, if node is waiting for another node to read or write a connection
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*/
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module node (
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input clk, // clock
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input rst, // reset
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input up_in[GNode.WORDLEN],
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output<G_nodeCon.nodeConIn> up_out,
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input right_in[GNode.WORDLEN],
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output<G_nodeCon.nodeConIn> right_out,
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input down_in[GNode.WORDLEN],
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output<G_nodeCon.nodeConIn> down_out,
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input left_in[GNode.WORDLEN],
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output<G_nodeCon.nodeConIn> left_out,
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output error,
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input subclk
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) {
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.clk(clk), .rst(rst) {
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dff pc[4](#INIT(0)); //program counter
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dff<GNode.cmd> cmds[GNode.ROWS];
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dff lastreg[3](#INIT(0)); // default = NIL
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dff acc[GNode.WORDLEN](#INIT(0));
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dff bak[GNode.WORDLEN](#INIT(0));
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dff is_reading(#INIT(0));
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dff is_writing(#INIT(0));
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dff<GNode.cmd> currentCmd;
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fsm currentCmdFSM = {MOV, // 2 args: 1const, 1reg or 2 reg
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JEZ, JNZ, JGZ, JLZ, JRO, // 1 arg: 5bit(signed) const offset
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ADD, SUB, // 1 arg: 1reg or 1 signed const
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NEG, SWP, SAV}; // no arg
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dff currentCmd_has_const(#INIT(0));
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dff currentCmd_const[GNode.WORDLEN](#INIT(0));
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dff currentCmd_has_reg[2](#INIT(0)); // only mov has two arguments (dst ist first; src ist second)
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dff currentCmd_reg[2][3];//registers to use TODO: add #INIT(0)
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registerMultiplex reg1(.selection(currentCmd_reg[0]), .acc(acc), .up(up), .right(right), .down(down), .left(left), .last(lastreg));
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}
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always {
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error = 0;
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if(subclk == 0 && is_reading.q == 0 && is_writing.q == 0) {
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//read command
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currentCmd.d = cmds.q[pc.q];
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currentCmdFSM.d = cmds.q[pc.q];
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} else if(subclk == 1 && is_reading.q == 0 && is_writing.q == 0) {
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//interpret
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//set them for all commands just set the _has_ flag if reguired
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currentCmd_reg.d[0] = currentCmd.q.args[ GNode.REGISTERADDRLEN -1 : 0]; //3 LSB bytes = register 1
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currentCmd_reg.d[1] = currentCmd.q.args[(2*GNode.REGISTERADDRLEN) -1 : GNode.REGISTERADDRLEN]; //3 next bytes = register 2
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currentCmd_const.d = currentCmd.q.args;
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//set the _has_ flags
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currentCmd_has_const.d = (currentCmdFSM.q >= currentCmdFSM.JEZ && currentCmdFSM.q <= currentCmdFSM.JLZ) || currentCmd.q.arg_is_const == 1; //last bit of cmd indicates a constant for cmd's that can do both
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currentCmd_has_reg.d[0] = (currentCmdFSM.q == currentCmdFSM.MOV || currentCmd.q.arg_is_const == 0); //mov cmd -> at least 1 reg or no constant
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currentCmd_has_reg.d[1] = (currentCmdFSM.q == currentCmdFSM.MOV && currentCmd.q.arg_is_const == 0); //mov cmd und arg ist keine constante -> 2 register
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} else if(subclk == 2 && is_reading.q == 0 && is_writing.q == 0) {
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//mark input as read
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is_reading.d = 1;
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}
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}
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/**
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A Connection between two Nodes, blocks
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*/
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global G_nodeCon {
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const WIDTH = 10;
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struct nodeConIn {
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write,
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read,
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enable,
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in[WIDTH]
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}
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}
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module nodeCon (
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input clk, // clock
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input rst, // reset
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input<G_nodeCon.nodeConIn> a_in,
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output a_out[G_nodeCon.WIDTH],
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output done, //erledigt (blokirung kann uafgehoben werden)
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/*input b_write,
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input b_read,
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input b_enable,
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input b_in[WIDTH],*/
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input<G_nodeCon.nodeConIn> b_in,
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output b_out[G_nodeCon.WIDTH],
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output error
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) {
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dff internalBuff[G_nodeCon.WIDTH](#INIT(0), .clk(clk), .rst(rst));
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always {
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error = ((a_in.write && b_in.write) || (a_in.read && b_in.read)) && ~rst && a_in.enable && b_in.enable; // gleichzeitiges lesen oder schreiben und nicht reset
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done = (a_in.write && b_in.write) || (a_in.read && b_in.write) && a_in.enable && b_in.enable;
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a_out = 0;
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if(a_in.enable) {
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if(a_in.write) {
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internalBuff.d = a_in;
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} else if(a_in.read) {
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a_out = internalBuff.q;
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}
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}
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b_out = 0;
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if(b_in.enable) {
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if(b_in.write) {
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internalBuff.d = b_in;
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} else if(b_in.read) {
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b_out = internalBuff.q;
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}
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}
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}
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}
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module registerMultiplex (
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input clk, // clock
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input rst, // reset
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input selection[3], //which register? see node.luc for enumeration
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input acc[GNode.WORDLEN],
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input up[GNode.WORDLEN],
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input right[GNode.WORDLEN],
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input down[GNode.WORDLEN],
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input left[GNode.WORDLEN],
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input last[GNode.REGISTERADDRLEN], //CAREFULL! this is NOT a register! this is a address!
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input any[GNode.WORDLEN],
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output out[GNode.WORDLEN],
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input in[GNode.WORDLEN],
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input write,
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input read
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) {
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dff outb[GNode.WORDLEN](.clk(clk), .rst(rst), #INIT(0));
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always {
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//reading
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if(read) {
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if(selection == 0) {
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outb.d = 0;
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} else if(selection == 1) {
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outb.d = acc;
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} else if(selection == 2) {
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outb.d = up;
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} else if(selection == 3) {
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outb.d = right;
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} else if(selection == 4) {
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outb.d = down;
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} else if(selection == 5) {
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outb.d = left;
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} else if(selection == 6) {
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if(last == 0) { //inenr selection for last
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}
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} else if(selection == 7) {
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outb.d = any;
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} else {
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outb.d = 0;
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}
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} else {
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outb.d = 0;
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}
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out = outb.q;
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if(write) {
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//TODO: fwd in to the register and set writing flags
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}
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}
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}
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module tis100 (
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input clk, // clock
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input rst, // reset
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output out
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) {
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always {
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out = 0;
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}
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}
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<?xml version="1.0" encoding="UTF-8"?>
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<project name="tis-100" board="Mojo" language="Lucid" version="2">
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<files>
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<src>node.luc</src>
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<src>tis100.luc</src>
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<src top="true">mojo_top.luc</src>
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<src>nodeCon.luc</src>
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<src>registerMultiplex.luc</src>
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<component>reset_conditioner.luc</component>
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<constraint lib="true">mojo.ucf</constraint>
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</files>
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</project>
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