TIS-100-FPGA/source/registerMultiplex.luc

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module registerMultiplex (
input clk, // clock
input rst, // reset
input selection[3], //which register? see node.luc for enumeration
input acc[GNode.WORDLEN],
input up[GNode.WORDLEN],
input right[GNode.WORDLEN],
input down[GNode.WORDLEN],
input left[GNode.WORDLEN],
input last[GNode.REGISTERADDRLEN], //CAREFULL! this is NOT a register! this is a address!
input any[GNode.WORDLEN],
output out[GNode.WORDLEN],
input in[GNode.WORDLEN],
input write,
input read
) {
dff outb[GNode.WORDLEN](.clk(clk), .rst(rst), #INIT(0));
always {
//reading
if(read) {
if(selection == 0) {
outb.d = 0;
} else if(selection == 1) {
outb.d = acc;
} else if(selection == 2) {
outb.d = up;
} else if(selection == 3) {
outb.d = right;
} else if(selection == 4) {
outb.d = down;
} else if(selection == 5) {
outb.d = left;
} else if(selection == 6) {
if(last == 0) { //inenr selection for last
}
} else if(selection == 7) {
outb.d = any;
} else {
outb.d = 0;
}
} else {
outb.d = 0;
}
out = outb.q;
if(write) {
//TODO: fwd in to the register and set writing flags
}
}
}