ready for first tests, not working ofcourse
This commit is contained in:
parent
e1227820dd
commit
277a86ea64
GPG Key ID:
596B2350DCD67504
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@ -14,18 +14,35 @@ module mojo_top (
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) {
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sig rst; // reset signal
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sig clk2;
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sig subclk[3]; //alows for 8 subclock pulses
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.clk(clk) {
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// The reset conditioner is used to synchronize the reset signal to the FPGA
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// clock. This ensures the entire FPGA comes out of reset at the same time.
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reset_conditioner reset_cond;
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.rst(rst) {
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counter slow_clk(#SIZE(15), #DIV(15));
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}
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}
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.clk(clk2), .rst(rst), .subclk(subclk) {
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node nodeA(.up_in(GNode.NULL), .right_in(GNode.NULL), .down_in(GNode.NULL), .left_in(GNode.NULL));
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}
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always {
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reset_cond.in = ~rst_n; // input raw inverted reset signal
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rst = reset_cond.out; // conditioned reset
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led = 8h00; // turn LEDs off
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clk2 = slow_clk.value[11];
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subclk = slow_clk.value[13:11];
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led = c{nodeA.left_out.in[3:0], subclk, clk2};
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// led = 8h00; // turn LEDs off
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spi_miso = bz; // not using SPI
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spi_channel = bzzzz; // not using flags
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avr_rx = bz; // not using serial port
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194
source/node.luc
194
source/node.luc
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@ -5,6 +5,8 @@ global GNode {
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const WORDLEN = 11; //bits to store a number (-999 to 999)
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const REGISTERADDRLEN = 3; //bits to address a register
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const NULL = 11h0;
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struct cmd {
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cmd[4],
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arg_is_const, //1 = argument is a 11bit signed integer, 0 argument is a register number
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@ -22,17 +24,18 @@ Register numbers:
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3 = RIGHT
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4 = DOWN
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5 = LEFT
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6 = LAST
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7 = ANY
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6 = LAST (not implemented correctly)
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7 = ANY (not implemented correctly)
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Subclk:
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Subclk: (a counter that steps every clock cycle to execute one part of an command)
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0 = Read cmd
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1 = interpret cmd
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2 = Mark input as read
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3 = try to read
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4 = mark output as read
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5 = write to output
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6 = increment pc and reset everything thats not needed anymore
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4 = calculate
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5 = mark output as read
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6 = write to output
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7 = increment pc and reset everything thats not needed anymore and update last register special case: regiuster == 6!
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cycles are skiped, if node is waiting for another node to read or write a connection
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*/
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@ -54,42 +57,96 @@ module node (
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output<G_nodeCon.nodeConIn> left_out,
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output error,
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input subclk
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input subclk[3]
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) {
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sig to_reg[GNode.WORDLEN];
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sig read_reg;
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sig write_reg;
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sig i[$clog2(GNode.ROWS)]; //DEBUG ONLY, counter variable for a for-loop
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signed sig mainarg[GNode.WORDLEN]; //always reading
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//sig argtwo[GNode.WORDLEN]; //always writing (mov cmd)
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.clk(clk), .rst(rst) {
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dff pc[4](#INIT(0)); //program counter
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dff<GNode.cmd> cmds[GNode.ROWS];
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dff lastreg[3](#INIT(0)); // default = NIL
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dff acc[GNode.WORDLEN](#INIT(0));
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dff bak[GNode.WORDLEN](#INIT(0));
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dff is_reading(#INIT(0));
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dff is_writing(#INIT(0));
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dff<GNode.cmd> currentCmd;
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fsm currentCmdFSM = {MOV, // 2 args: 1const, 1reg or 2 reg
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JEZ, JNZ, JGZ, JLZ, JRO, // 1 arg: 5bit(signed) const offset
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JEZ, JNZ, JGZ, JLZ, JRO, // 1 arg: 5bit(signed) const offset
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ADD, SUB, // 1 arg: 1reg or 1 signed const
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NEG, SWP, SAV}; // no arg
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dff currentCmd_has_const(#INIT(0));
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dff currentCmd_const[GNode.WORDLEN](#INIT(0));
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dff currentCmd_has_reg[2](#INIT(0)); // only mov has two arguments (dst ist first; src ist second)
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dff currentCmd_reg[2][3];//registers to use TODO: add #INIT(0)
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registerMultiplex reg1(.selection(currentCmd_reg[0]), .acc(acc), .up(up), .right(right), .down(down), .left(left), .last(lastreg));
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#INIT(0) {
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dff currentCmd_has_const;
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signed dff currentCmd_const[GNode.WORDLEN];
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dff currentCmd_has_reg[2]; // only mov has two arguments (dst ist first (every cmd); src ist second(only used for mov))
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dff lastreg[3]; // which register to use with LAST keyword, default = NIL
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signed dff acc[GNode.WORDLEN];
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signed dff bak[GNode.WORDLEN];
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dff is_reading; //is command reading from a register? reading from ACC or BAK may not count (depending on context)
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dff is_writing; //is command writing to a register? writing to ACC or BAK may not count (should be a pseudonym for currentCmd == MOV)
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dff is_reading_inProgress; //is reading or writing in progress? (block every thing then)
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dff is_writing_inProgress; //only on of this two can be 1 !
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dff pc[4]; //program counter (which instruction to execute?)
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}
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dff currentCmd_reg[2][3];//registers to use TODO: add #INIT(0)
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//TODO: fix selection! - when select what as read or as write reg?
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registerDemultiplex reg_read(.selection(currentCmd_reg.q[0]), .acc(acc.q), .up(up_in), .right(right_in), .down(down_in), .left(left_in), .last(lastreg.q), .any(11h0), .read(read_reg));
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registerMultiplex reg_write(.selection(currentCmd_reg.q[1]), .lastadr(lastreg.q), .write(write_reg), .in(to_reg));
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}
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always {
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error = 0;
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if(subclk == 0 && is_reading.q == 0 && is_writing.q == 0) {
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//EXAMPLE CODE
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//ADD 1
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cmds.d[0].cmd = currentCmdFSM.ADD;
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cmds.d[0].arg_is_const = 1;
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cmds.d[0].args = 11d1; //1
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//MOV ACC, LEFT
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cmds.d[1].cmd = currentCmdFSM.MOV;
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cmds.d[1].arg_is_const = 0;
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cmds.d[1].args = 11b0101001; //0 5 1 (leer, left, acc) von acc -> left
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//write NULL-OP's to the rest of memory
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for(i = 2; i < GNode.ROWS; i++) {
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cmds.d[1].cmd = currentCmdFSM.ADD;
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cmds.d[1].arg_is_const = 1;
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cmds.d[1].args = 11h0;
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}
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error = 0; // no error
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read_reg = 0; //default to non reading
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//define outputs
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up_out.in = reg_write.up;
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up_out.write = reg_write.up_w;
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right_out.in = reg_write.right;
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right_out.write = reg_write.right_w;
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down_out.in = reg_write.down;
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down_out.write = reg_write.down_w;
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left_out.in = reg_write.left;
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left_out.write = reg_write.left_w;
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if(subclk == 0 && is_reading_inProgress.q == 0 && is_writing_inProgress.q == 0) {
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//read command
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currentCmd.d = cmds.q[pc.q];
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currentCmdFSM.d = cmds.q[pc.q];
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} else if(subclk == 1 && is_reading.q == 0 && is_writing.q == 0) {
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} else if(subclk == 1 && is_reading_inProgress.q == 0 && is_writing_inProgress.q == 0) {
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//interpret
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//set them for all commands just set the _has_ flag if reguired
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@ -101,10 +158,89 @@ module node (
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currentCmd_has_const.d = (currentCmdFSM.q >= currentCmdFSM.JEZ && currentCmdFSM.q <= currentCmdFSM.JLZ) || currentCmd.q.arg_is_const == 1; //last bit of cmd indicates a constant for cmd's that can do both
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currentCmd_has_reg.d[0] = (currentCmdFSM.q == currentCmdFSM.MOV || currentCmd.q.arg_is_const == 0); //mov cmd -> at least 1 reg or no constant
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currentCmd_has_reg.d[1] = (currentCmdFSM.q == currentCmdFSM.MOV && currentCmd.q.arg_is_const == 0); //mov cmd und arg ist keine constante -> 2 register
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} else if(subclk == 2 && is_reading.q == 0 && is_writing.q == 0) {
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//mark input as read
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is_reading.d = 1;
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//set flags for reading and writing
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is_reading.d = (currentCmdFSM.q == currentCmdFSM.MOV || ((currentCmdFSM.q == currentCmdFSM.ADD || currentCmdFSM.q == currentCmdFSM.SUB) && currentCmd_has_const.q == 0)); //mov cmd or add/sub in register mode
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is_writing.d = (currentCmdFSM.q == currentCmdFSM.MOV); //only mov cmd can write to a register aparently
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} else if(subclk == 2 && is_reading_inProgress.q == 0 && is_writing_inProgress.q == 0) {
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//mark input as read
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if(is_reading.q == 1) {
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//do reading stuff
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//TODO: this
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read_reg = 1;
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}
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} else if(subclk == 3 && is_writing_inProgress.q == 0) {
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//reading
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if(is_reading.q == 1) {
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read_reg = 1; //try to read the register NOW
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is_reading_inProgress.d = ~reg_read.done; //wenn fertig -> kein read mehr in progress, sonst: nächsten zyklus nochmal
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}
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} else if(subclk == 4 && is_reading_inProgress.q == 0 && is_writing_inProgress.q == 0) {
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//calculate
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//args
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mainarg = currentCmd_has_const.q ? currentCmd_const.q : reg_read.out;
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case (currentCmdFSM.q) {
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currentCmdFSM.MOV:
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to_reg = mainarg;
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write_reg = 1;
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is_writing_inProgress.d = 1;
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currentCmdFSM.JEZ: //jump equals Zero
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if (acc.q == 0) {
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//jump
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pc.d = pc.q + mainarg;
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}
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currentCmdFSM.JNZ: //jump not equals zero
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if(acc.q != 0) {
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//jump
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pc.d = pc.q + mainarg;
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}
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currentCmdFSM.JGZ: //jmp greater zero
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if(acc.q > 0) {
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pc.d = pc.q + mainarg;
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}
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currentCmdFSM.JLZ: //jmp less zero
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if(acc.q < 0) {
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pc.d = pc.q + mainarg;
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}
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currentCmdFSM.JRO: //jmp ro (offset) unconditional
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pc.d = pc.q + mainarg;
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currentCmdFSM.ADD:
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acc.d = acc.q + mainarg;
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currentCmdFSM.SUB:
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acc.d = acc.q - mainarg;
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currentCmdFSM.NEG:
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acc.d = -acc.q;
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currentCmdFSM.SWP:
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bak.d = acc.q; //does this work?
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acc.d = bak.q;
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currentCmdFSM.SAV:
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bak.d = acc.q;
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}
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} else if(subclk == 7 && is_reading_inProgress.q == 0 && is_writing_inProgress.q == 0) {
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//increment pc
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if(pc.q + 1 >= GNode.ROWS) {
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pc.d = 0; //loop over
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} else {
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pc.d = pc.q + 1;
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}
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//reset everything
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}
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}
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@ -6,13 +6,13 @@
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*/
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global G_nodeCon {
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const WIDTH = 10;
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const WIDTH = 11;
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struct nodeConIn {
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write,
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read,
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enable,
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in[WIDTH]
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signed in[WIDTH]
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}
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}
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@ -22,7 +22,7 @@ module nodeCon (
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input rst, // reset
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input<G_nodeCon.nodeConIn> a_in,
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output a_out[G_nodeCon.WIDTH],
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signed output a_out[GNode.WORDLEN],
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output done, //erledigt (blokirung kann uafgehoben werden)
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@ -31,9 +31,9 @@ module nodeCon (
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input b_enable,
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input b_in[WIDTH],*/
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input<G_nodeCon.nodeConIn> b_in,
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output b_out[G_nodeCon.WIDTH],
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signed output b_out[G_nodeCon.WIDTH],
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output error
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output error //output 1 on deadlock
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) {
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dff internalBuff[G_nodeCon.WIDTH](#INIT(0), .clk(clk), .rst(rst));
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@ -0,0 +1,74 @@
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/**
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Takes many registers and only reads from ONE selected
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*/
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module registerDemultiplex (
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input clk, // clock
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input rst, // reset
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input selection[3], //which register? see node.luc for enumeration
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input acc[GNode.WORDLEN],
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input up[GNode.WORDLEN],
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input right[GNode.WORDLEN],
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input down[GNode.WORDLEN],
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input left[GNode.WORDLEN],
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input last[GNode.REGISTERADDRLEN], //CAREFULL! this is NOT a register! this is a address!
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input any[GNode.WORDLEN],
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output out[GNode.WORDLEN],
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output done, //TODO: implement this fully
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input read
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) {
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dff outb[GNode.WORDLEN](.clk(clk), .rst(rst), #INIT(0));
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always {
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//reading
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done = 0;
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if(read) {
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if(selection == 0) {
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outb.d = 0;
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done = 1;
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} else if(selection == 1) {
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outb.d = acc;
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done = 1;
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} else if(selection == 2) {
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outb.d = up;
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} else if(selection == 3) {
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outb.d = right;
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} else if(selection == 4) {
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outb.d = down;
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} else if(selection == 5) {
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outb.d = left;
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} else if(selection == 6) {
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//inner selection for last register
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case (last) {
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0: outb.d = 0; //NIL
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done = 1;
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1: outb.d = acc;
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2: outb.d = up;
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3: outb.d = right;
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4: outb.d = down;
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5: outb.d = left;
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7: outb.d = 0; //ANY - not implemented correctly!
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done = 1;
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}
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} else if(selection == 7) {
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outb.d = any;
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} else {
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outb.d = 0;
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done = 0;
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}
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} else {
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outb.d = 0;
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done = 0;
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}
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out = outb.q;
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}
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}
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@ -1,3 +1,10 @@
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/**
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Takes a value and many registers and writes the value to one specified register
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*/
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module registerMultiplex (
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input clk, // clock
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input rst, // reset
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@ -5,54 +12,44 @@ module registerMultiplex (
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input selection[3], //which register? see node.luc for enumeration
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input acc[GNode.WORDLEN],
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input up[GNode.WORDLEN],
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input right[GNode.WORDLEN],
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input down[GNode.WORDLEN],
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input left[GNode.WORDLEN],
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input last[GNode.REGISTERADDRLEN], //CAREFULL! this is NOT a register! this is a address!
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input any[GNode.WORDLEN],
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output acc[GNode.WORDLEN],
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output up[GNode.WORDLEN],
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output right[GNode.WORDLEN],
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output down[GNode.WORDLEN],
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output left[GNode.WORDLEN],
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input lastadr[GNode.REGISTERADDRLEN], //CAUTION! JUST AN ADDRESS!
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output any[GNode.WORDLEN],
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output acc_w,
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output up_w,
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output right_w,
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output down_w,
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output left_w,
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output any_w,
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output out[GNode.WORDLEN],
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input in[GNode.WORDLEN],
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input write,
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input read
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input write
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) {
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dff outb[GNode.WORDLEN](.clk(clk), .rst(rst), #INIT(0));
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always {
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//reading
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if(read) {
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if(selection == 0) {
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outb.d = 0;
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} else if(selection == 1) {
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outb.d = acc;
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} else if(selection == 2) {
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outb.d = up;
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} else if(selection == 3) {
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outb.d = right;
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} else if(selection == 4) {
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outb.d = down;
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} else if(selection == 5) {
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outb.d = left;
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} else if(selection == 6) {
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if(last == 0) { //inenr selection for last
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}
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} else if(selection == 7) {
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outb.d = any;
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} else {
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||||
outb.d = 0;
|
||||
}
|
||||
} else {
|
||||
outb.d = 0;
|
||||
}
|
||||
out = outb.q;
|
||||
acc_w = write && selection == 1;
|
||||
up_w = write && selection == 2;
|
||||
right_w = write && selection == 3;
|
||||
down_w = write && selection == 4;
|
||||
left_w = write && selection == 5;
|
||||
any_w = write && selection == 7;
|
||||
|
||||
if(write) {
|
||||
//TODO: fwd in to the register and set writing flags
|
||||
acc = selection == 1 ? in : 0;
|
||||
up = selection == 2 ? in : 0;
|
||||
right = selection == 3 ? in : 0;
|
||||
down = selection == 4 ? in : 0;
|
||||
left = selection == 5 ? in : 0;
|
||||
any = selection == 7 ? in : 0;
|
||||
|
||||
if(write && selection == 6) {
|
||||
//last register
|
||||
|
||||
//TODO: this
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<project name="tis-100" board="Mojo" language="Lucid" version="2">
|
||||
<files>
|
||||
<src>registerDemultiplex.luc</src>
|
||||
<component>counter.luc</component>
|
||||
<src>node.luc</src>
|
||||
<src>tis100.luc</src>
|
||||
<src top="true">mojo_top.luc</src>
|
||||
|
|
|
|||
Loading…
Reference in New Issue