PPC: convert Altivec FFT to pure assembler
On PPC a leaf function has a 288-byte red zone below the stack pointer, sparing these functions the chore of setting up a full stack frame. When a function call is disguised within an inline asm block, the compiler might not adjust the stack pointer as required before a function call, resulting in the red zone being clobbered. Moving the entire function to pure asm avoids this problem and also results in somewhat better code. Originally committed as revision 24044 to svn://svn.ffmpeg.org/ffmpeg/trunk
This commit is contained in:
Måns Rullgård
parent
deca86eab1
commit
a46b84d120
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@ -22,7 +22,6 @@
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#include "libavcodec/fft.h"
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#include "util_altivec.h"
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#include "types_altivec.h"
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#include "regs.h"
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/**
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* Do a complex FFT with the parameters defined in ff_fft_init(). The
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@ -33,51 +32,10 @@
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* It also assumes all FFTComplex are 8 bytes-aligned pair of float
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*/
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// Pointers to functions. Not using function pointer syntax, because
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// that involves an extra level of indirection on some PPC ABIs.
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extern void *ff_fft_dispatch_altivec[2][15];
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void ff_fft_calc_altivec(FFTContext *s, FFTComplex *z);
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void ff_fft_calc_interleave_altivec(FFTContext *s, FFTComplex *z);
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#if HAVE_GNU_AS
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static av_always_inline void fft_dispatch(FFTContext *s, FFTComplex *z, int do_swizzle)
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{
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register vec_f v14 __asm__("v14") = {0,0,0,0};
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register vec_f v15 __asm__("v15") = *(const vec_f*)ff_cos_16;
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register vec_f v16 __asm__("v16") = {0, 0.38268343, M_SQRT1_2, 0.92387953};
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register vec_f v17 __asm__("v17") = {-M_SQRT1_2, M_SQRT1_2, M_SQRT1_2,-M_SQRT1_2};
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register vec_f v18 __asm__("v18") = { M_SQRT1_2, M_SQRT1_2, M_SQRT1_2, M_SQRT1_2};
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register vec_u8 v19 __asm__("v19") = vcprm(s0,3,2,1);
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register vec_u8 v20 __asm__("v20") = vcprm(0,1,s2,s1);
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register vec_u8 v21 __asm__("v21") = vcprm(2,3,s0,s3);
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register vec_u8 v22 __asm__("v22") = vcprm(2,s3,3,s2);
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register vec_u8 v23 __asm__("v23") = vcprm(0,1,s0,s1);
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register vec_u8 v24 __asm__("v24") = vcprm(2,3,s2,s3);
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register vec_u8 v25 __asm__("v25") = vcprm(2,3,0,1);
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register vec_u8 v26 __asm__("v26") = vcprm(1,2,s3,s0);
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register vec_u8 v27 __asm__("v27") = vcprm(0,3,s2,s1);
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register vec_u8 v28 __asm__("v28") = vcprm(0,2,s1,s3);
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register vec_u8 v29 __asm__("v29") = vcprm(1,3,s0,s2);
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register FFTSample *const*cos_tabs __asm__("r12") = ff_cos_tabs;
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register FFTComplex *zarg __asm__("r3") = z;
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__asm__(
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"mtctr %0 \n"
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"li "r(9)", 16 \n"
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"subi "r(1)","r(1) ",%1 \n"
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"bctrl \n"
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"addi "r(1)","r(1) ",%1 \n"
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::"r"(ff_fft_dispatch_altivec[do_swizzle][s->nbits-2]), "i"(12*sizeof(void*)),
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"r"(zarg), "r"(cos_tabs),
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"v"(v14),"v"(v15),"v"(v16),"v"(v17),"v"(v18),"v"(v19),"v"(v20),"v"(v21),
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"v"(v22),"v"(v23),"v"(v24),"v"(v25),"v"(v26),"v"(v27),"v"(v28),"v"(v29)
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: "lr","ctr","r0","r4","r5","r6","r7","r8","r9","r10","r11",
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"v0","v1","v2","v3","v4","v5","v6","v7","v8","v9","v10","v11","v12","v13"
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);
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}
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static void ff_fft_calc_altivec(FFTContext *s, FFTComplex *z)
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{
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fft_dispatch(s, z, 1);
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}
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static void ff_imdct_half_altivec(FFTContext *s, FFTSample *output, const FFTSample *input)
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{
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int j, k;
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@ -132,7 +90,7 @@ static void ff_imdct_half_altivec(FFTContext *s, FFTSample *output, const FFTSam
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k--;
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} while(k >= 0);
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fft_dispatch(s, (FFTComplex*)output, 0);
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ff_fft_calc_altivec(s, (FFTComplex*)output);
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/* post rotation + reordering */
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j = -n32;
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@ -182,7 +140,7 @@ static void ff_imdct_calc_altivec(FFTContext *s, FFTSample *output, const FFTSam
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av_cold void ff_fft_init_altivec(FFTContext *s)
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{
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#if HAVE_GNU_AS
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s->fft_calc = ff_fft_calc_altivec;
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s->fft_calc = ff_fft_calc_interleave_altivec;
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s->imdct_calc = ff_imdct_calc_altivec;
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s->imdct_half = ff_imdct_half_altivec;
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#endif
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@ -49,24 +49,6 @@
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.endif
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.endm
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#if ARCH_PPC64
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#define PTR .quad
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.macro LOAD_PTR ra, rbase, offset
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ld \ra,(\offset)*8(\rbase)
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.endm
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.macro STORE_PTR ra, rbase, offset
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std \ra,(\offset)*8(\rbase)
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.endm
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#else
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#define PTR .int
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.macro LOAD_PTR ra, rbase, offset
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lwz \ra,(\offset)*4(\rbase)
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.endm
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.macro STORE_PTR ra, rbase, offset
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stw \ra,(\offset)*4(\rbase)
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.endm
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#endif
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.macro FFT4 a0, a1, a2, a3 // in:0-1 out:2-3
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vperm \a2,\a0,\a1,v20 // vcprm(0,1,s2,s1) // {r0,i0,r3,i2}
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vperm \a3,\a0,\a1,v21 // vcprm(2,3,s0,s3) // {r1,i1,r2,i3}
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@ -314,18 +296,105 @@ fft_pass\suffix\()_altivec:
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blr
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.endm
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#define M_SQRT1_2 0.70710678118654752440 /* 1/sqrt(2) */
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#define WORD_0 0x00,0x01,0x02,0x03
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#define WORD_1 0x04,0x05,0x06,0x07
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#define WORD_2 0x08,0x09,0x0a,0x0b
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#define WORD_3 0x0c,0x0d,0x0e,0x0f
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#define WORD_s0 0x10,0x11,0x12,0x13
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#define WORD_s1 0x14,0x15,0x16,0x17
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#define WORD_s2 0x18,0x19,0x1a,0x1b
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#define WORD_s3 0x1c,0x1d,0x1e,0x1f
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#define vcprm(a, b, c, d) .byte WORD_##a, WORD_##b, WORD_##c, WORD_##d
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.rodata
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.align 4
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fft_data:
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.float 0, 0, 0, 0
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.float 1, 0.92387953, M_SQRT1_2, 0.38268343
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.float 0, 0.38268343, M_SQRT1_2, 0.92387953
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.float -M_SQRT1_2, M_SQRT1_2, M_SQRT1_2,-M_SQRT1_2
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.float M_SQRT1_2, M_SQRT1_2, M_SQRT1_2, M_SQRT1_2
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vcprm(s0,3,2,1)
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vcprm(0,1,s2,s1)
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vcprm(2,3,s0,s3)
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vcprm(2,s3,3,s2)
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vcprm(0,1,s0,s1)
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vcprm(2,3,s2,s3)
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vcprm(2,3,0,1)
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vcprm(1,2,s3,s0)
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vcprm(0,3,s2,s1)
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vcprm(0,2,s1,s3)
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vcprm(1,3,s0,s2)
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.macro lvm b, r, regs:vararg
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lvx \r, 0, \b
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addi \b, \b, 16
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.ifnb \regs
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lvm \b, \regs
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.endif
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.endm
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.macro stvm b, r, regs:vararg
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stvx \r, 0, \b
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addi \b, \b, 16
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.ifnb \regs
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stvm \b, \regs
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.endif
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.endm
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.macro fft_calc interleave
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extfunc ff_fft_calc\interleave\()_altivec
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mflr r0
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stp r0, 2*PS(r1)
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stpu r1, -(160+16*PS)(r1)
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addi r6, r1, 16*PS
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stvm r6, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29
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mfvrsave r0
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stw r0, 15*PS(r1)
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li r6, 0xfffffffc
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mtvrsave r6
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movrel r6, fft_data
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lvm r6, v14, v15, v16, v17, v18, v19, v20, v21
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lvm r6, v22, v23, v24, v25, v26, v27, v28, v29
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li r9, 16
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movrel r12, X(ff_cos_tabs)
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movrel r6, fft_dispatch_tab\interleave\()_altivec
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lwz r3, 0(r3)
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subi r3, r3, 2
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slwi r3, r3, 2+ARCH_PPC64
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lpx r3, r3, r6
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mtctr r3
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mr r3, r4
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bctrl
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addi r6, r1, 16*PS
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lvm r6, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29
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lwz r6, 15*PS(r1)
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mtvrsave r6
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lp r1, 0(r1)
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lp r0, 2*PS(r1)
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mtlr r0
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blr
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.endm
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.macro DECL_FFT suffix, bits, n, n2, n4
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fft\n\suffix\()_altivec:
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mflr r0
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STORE_PTR r0,r1,\bits-5
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stp r0,PS*(\bits-3)(r1)
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bl fft\n2\()_altivec
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addi2 r3,\n*4
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bl fft\n4\()_altivec
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addi2 r3,\n*2
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bl fft\n4\()_altivec
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addi2 r3,\n*-6
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LOAD_PTR r0,r1,\bits-5
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LOAD_PTR r4,r12,\bits
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lp r0,PS*(\bits-3)(r1)
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lp r4,\bits*PS(r12)
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mtlr r0
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li r5,\n/16
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b fft_pass\suffix\()_altivec
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@ -350,9 +419,11 @@ fft\n\suffix\()_altivec:
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DECL_FFT \suffix,15,32768,16384, 8192
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DECL_FFT \suffix,16,65536,32768,16384
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fft_calc \suffix
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.rodata
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.global EXTERN_ASM\()ff_fft_dispatch\suffix\()_altivec
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EXTERN_ASM\()ff_fft_dispatch\suffix\()_altivec:
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.align 3
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fft_dispatch_tab\suffix\()_altivec:
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PTR fft4\suffix\()_altivec
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PTR fft8\suffix\()_altivec
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PTR fft16\suffix\()_altivec
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