x86/hevc_idct: replace old and unused idct functions
Only 8-bit and 10-bit idct_dc() functions are included (adding others should be trivial).
Benchmarks on an Intel Core i5-4200U:
idct8x8_dc
SSE2 MMXEXT C
cycles 22 26 57
idct16x16_dc
AVX2 SSE2 C
cycles 27 32 249
idct32x32_dc
AVX2 SSE2 C
cycles 62 126 1375
Signed-off-by: James Almer <jamrial@gmail.com>
Reviewed-by: Mickaël Raulet <mraulet@gmail.com>
Signed-off-by: Michael Niedermayer <michaelni@gmx.at>
This commit is contained in:
James Almer
Michael Niedermayer
parent
23480da0aa
commit
1ace9573dc
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@ -56,8 +56,6 @@ typedef struct HEVCDSPContext {
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void (*idct_dc[4])(int16_t *coeffs);
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void (*transform_dc_add[4])(uint8_t *dst, int16_t *coeffs, ptrdiff_t stride);
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void (*sao_band_filter)(uint8_t *_dst, uint8_t *_src, ptrdiff_t _stride_dst, ptrdiff_t _stride_src,
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struct SAOParams *sao, int *borders,
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int width, int height, int c_idx);
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@ -1,6 +1,7 @@
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; /*
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; * Provide SSE & MMX idct functions for HEVC decoding
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; * SIMD optimized idct functions for HEVC decoding
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; * Copyright (c) 2014 Pierre-Edouard LEPERE
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; * Copyright (c) 2014 James Almer
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; *
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; * This file is part of FFmpeg.
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; *
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@ -20,206 +21,86 @@
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; */
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%include "libavutil/x86/x86util.asm"
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SECTION_RODATA 32
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max_pixels_10: times 16 dw ((1 << 10)-1)
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dc_add_10: times 4 dd ((1 << 14-10) + 1)
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SECTION_TEXT 32
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;the idct_dc_add macros and functions were largely inspired by x264 project's code in the h264_idct.asm file
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%macro DC_ADD_INIT 2
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add %1w, ((1 << 14-8) + 1)
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sar %1w, (15-8)
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movd m0, %1d
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lea %1, [%2*3]
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SPLATW m0, m0, 0
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pxor m1, m1
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psubw m1, m0
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packuswb m0, m0
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packuswb m1, m1
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; void ff_hevc_idctHxW_dc_{8,10}_<opt>(int16_t *coeffs)
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; %1 = HxW
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; %2 = number of loops
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; %3 = bitdepth
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%macro IDCT_DC 3
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cglobal hevc_idct%1x%1_dc_%3, 1, 2, 1, coeff, tmp
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movsx tmpq, word [coeffq]
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add tmpw, ((1 << 14-%3) + 1)
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sar tmpw, (15-%3)
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movd xm0, tmpd
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SPLATW m0, xm0
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DEFINE_ARGS coeff, cnt
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mov cntd, %2
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.loop
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mova [coeffq+mmsize*0], m0
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mova [coeffq+mmsize*1], m0
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mova [coeffq+mmsize*2], m0
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mova [coeffq+mmsize*3], m0
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mova [coeffq+mmsize*4], m0
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mova [coeffq+mmsize*5], m0
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mova [coeffq+mmsize*6], m0
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mova [coeffq+mmsize*7], m0
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add coeffq, mmsize*8
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dec cntd
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jg .loop
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RET
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%endmacro
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%macro DC_ADD_INIT_AVX2 2
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add %1w, ((1 << 14-8) + 1)
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sar %1w, (15-8)
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movd xm0, %1d
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vpbroadcastw m0, xm0 ;SPLATW
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lea %1, [%2*3]
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pxor m1, m1
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psubw m1, m0
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packuswb m0, m0
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packuswb m1, m1
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%endmacro
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%macro DC_ADD_OP 4
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%1 m2, [%2 ]
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%1 m3, [%2+%3 ]
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%1 m4, [%2+%3*2]
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%1 m5, [%2+%4 ]
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paddusb m2, m0
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paddusb m3, m0
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paddusb m4, m0
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paddusb m5, m0
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psubusb m2, m1
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psubusb m3, m1
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psubusb m4, m1
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psubusb m5, m1
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%1 [%2 ], m2
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%1 [%2+%3 ], m3
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%1 [%2+%3*2], m4
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%1 [%2+%4 ], m5
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%endmacro
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INIT_MMX mmxext
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; void ff_hevc_idct_dc_add_8_mmxext(uint8_t *dst, int16_t *coeffs, ptrdiff_t stride)
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%if ARCH_X86_64
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cglobal hevc_idct4_dc_add_8, 3, 4, 0
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movsx r3, word [r1]
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DC_ADD_INIT r3, r2
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DC_ADD_OP movh, r0, r2, r3
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RET
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; void ff_hevc_idct8_dc_add_8_mmxext(uint8_t *dst, int16_t *coeffs, ptrdiff_t stride)
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cglobal hevc_idct8_dc_add_8, 3, 4, 0
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movsx r3, word [r1]
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DC_ADD_INIT r3, r2
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DC_ADD_OP mova, r0, r2, r3
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lea r0, [r0+r2*4]
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DC_ADD_OP mova, r0, r2, r3
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RET
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%else
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; void ff_hevc_idct_dc_add_8_mmxext(uint8_t *dst, int16_t *coeffs, ptrdiff_t stride)
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cglobal hevc_idct4_dc_add_8, 2, 3, 0
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movsx r2, word [r1]
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mov r1, r2m
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DC_ADD_INIT r2, r1
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DC_ADD_OP movh, r0, r1, r2
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RET
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; void ff_hevc_idct8_dc_add_8_mmxext(uint8_t *dst, int16_t *coeffs, ptrdiff_t stride)
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cglobal hevc_idct8_dc_add_8, 2, 3, 0
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movsx r2, word [r1]
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mov r1, r2m
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DC_ADD_INIT r2, r1
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DC_ADD_OP mova, r0, r1, r2
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lea r0, [r0+r1*4]
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DC_ADD_OP mova, r0, r1, r2
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RET
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; %1 = HxW
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; %2 = bitdepth
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%macro IDCT_DC_NL 2 ; No loop
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cglobal hevc_idct%1x%1_dc_%2, 1, 2, 1, coeff, tmp
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movsx tmpq, word [coeffq]
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add tmpw, ((1 << 14-%2) + 1)
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sar tmpw, (15-%2)
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movd m0, tmpd
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SPLATW m0, xm0
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mova [coeffq+mmsize*0], m0
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mova [coeffq+mmsize*1], m0
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mova [coeffq+mmsize*2], m0
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mova [coeffq+mmsize*3], m0
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%if mmsize == 16
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mova [coeffq+mmsize*4], m0
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mova [coeffq+mmsize*5], m0
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mova [coeffq+mmsize*6], m0
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mova [coeffq+mmsize*7], m0
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%endif
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RET
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%endmacro
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; 8-bit
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INIT_MMX mmxext
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IDCT_DC_NL 4, 8
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IDCT_DC 8, 2, 8
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INIT_XMM sse2
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; void ff_hevc_idct16_dc_add_8_sse2(uint8_t *dst, int16_t *coeffs, ptrdiff_t stride)
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cglobal hevc_idct16_dc_add_8, 3, 4, 6
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movsx r3, word [r1]
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DC_ADD_INIT r3, r2
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DC_ADD_OP mova, r0, r2, r3
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lea r0, [r0+r2*4]
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DC_ADD_OP mova, r0, r2, r3
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lea r0, [r0+r2*4]
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DC_ADD_OP mova, r0, r2, r3
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lea r0, [r0+r2*4]
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DC_ADD_OP mova, r0, r2, r3
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RET
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IDCT_DC_NL 8, 8
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IDCT_DC 16, 4, 8
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IDCT_DC 32, 16, 8
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%if HAVE_AVX2_EXTERNAL
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INIT_YMM avx2
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; void ff_hevc_idct32_dc_add_8_avx2(uint8_t *dst, int16_t *coeffs, ptrdiff_t stride)
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cglobal hevc_idct32_dc_add_8, 3, 4, 6
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movsx r3, word [r1]
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DC_ADD_INIT_AVX2 r3, r2
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DC_ADD_OP mova, r0, r2, r3,
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%rep 7
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lea r0, [r0+r2*4]
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DC_ADD_OP mova, r0, r2, r3
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%endrep
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RET
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IDCT_DC 16, 2, 8
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IDCT_DC 32, 8, 8
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%endif ;HAVE_AVX2_EXTERNAL
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;-----------------------------------------------------------------------------
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; void ff_hevc_idct_dc_add_10(pixel *dst, int16_t *block, int stride)
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;-----------------------------------------------------------------------------
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%macro IDCT_DC_ADD_OP_10 3
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pxor m5, m5
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%if avx_enabled
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paddw m1, m0, [%1+0 ]
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paddw m2, m0, [%1+%2 ]
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paddw m3, m0, [%1+%2*2]
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paddw m4, m0, [%1+%3 ]
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%else
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mova m1, [%1+0 ]
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mova m2, [%1+%2 ]
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mova m3, [%1+%2*2]
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mova m4, [%1+%3 ]
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paddw m1, m0
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paddw m2, m0
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paddw m3, m0
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paddw m4, m0
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%endif
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CLIPW m1, m5, m6
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CLIPW m2, m5, m6
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CLIPW m3, m5, m6
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CLIPW m4, m5, m6
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mova [%1+0 ], m1
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mova [%1+%2 ], m2
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mova [%1+%2*2], m3
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mova [%1+%3 ], m4
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%endmacro
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; 10-bit
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INIT_MMX mmxext
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cglobal hevc_idct4_dc_add_10,3,3
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mov r1w, [r1]
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add r1w, ((1 << 4) + 1)
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sar r1w, 5
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movd m0, r1d
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lea r1, [r2*3]
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SPLATW m0, m0, 0
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mova m6, [max_pixels_10]
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IDCT_DC_ADD_OP_10 r0, r2, r1
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RET
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;-----------------------------------------------------------------------------
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; void ff_hevc_idct8_dc_add_10(pixel *dst, int16_t *block, int stride)
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;-----------------------------------------------------------------------------
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%macro IDCT8_DC_ADD 0
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cglobal hevc_idct8_dc_add_10,3,4,7
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mov r1w, [r1]
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add r1w, ((1 << 4) + 1)
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sar r1w, 5
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movd m0, r1d
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lea r1, [r2*3]
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SPLATW m0, m0, 0
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mova m6, [max_pixels_10]
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IDCT_DC_ADD_OP_10 r0, r2, r1
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lea r0, [r0+r2*4]
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IDCT_DC_ADD_OP_10 r0, r2, r1
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RET
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%endmacro
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IDCT_DC_NL 4, 10
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IDCT_DC 8, 2, 10
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INIT_XMM sse2
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IDCT8_DC_ADD
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%if HAVE_AVX_EXTERNAL
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INIT_XMM avx
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IDCT8_DC_ADD
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%endif
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IDCT_DC_NL 8, 10
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IDCT_DC 16, 4, 10
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IDCT_DC 32, 16, 10
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%if HAVE_AVX2_EXTERNAL
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INIT_YMM avx2
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cglobal hevc_idct16_dc_add_10,3,4,7
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mov r1w, [r1]
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add r1w, ((1 << 4) + 1)
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sar r1w, 5
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movd xm0, r1d
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lea r1, [r2*3]
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vpbroadcastw m0, xm0 ;SPLATW
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mova m6, [max_pixels_10]
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IDCT_DC_ADD_OP_10 r0, r2, r1
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lea r0, [r0+r2*4]
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IDCT_DC_ADD_OP_10 r0, r2, r1
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lea r0, [r0+r2*4]
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IDCT_DC_ADD_OP_10 r0, r2, r1
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lea r0, [r0+r2*4]
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IDCT_DC_ADD_OP_10 r0, r2, r1
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RET
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%endif ;HAVE_AVX_EXTERNAL
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IDCT_DC 16, 2, 10
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IDCT_DC 32, 8, 10
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%endif ;HAVE_AVX2_EXTERNAL
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@ -131,32 +131,4 @@ WEIGHTING_PROTOTYPES(8, sse4);
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WEIGHTING_PROTOTYPES(10, sse4);
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WEIGHTING_PROTOTYPES(12, sse4);
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///////////////////////////////////////////////////////////////////////////////
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// IDCT
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///////////////////////////////////////////////////////////////////////////////
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idct_dc_proto(4, 8,mmxext);
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idct_dc_proto(8, 8,mmxext);
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idct_dc_proto(16,8, sse2);
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idct_dc_proto(32,8, sse2);
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idct_dc_proto(32,8, avx2);
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idct_dc_proto(4, 10,mmxext);
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idct_dc_proto(8, 10, sse2);
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idct_dc_proto(16,10, sse2);
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idct_dc_proto(32,10, sse2);
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idct_dc_proto(8, 10, avx);
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idct_dc_proto(16,10, avx);
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idct_dc_proto(32,10, avx);
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idct_dc_proto(16,10, avx2);
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idct_dc_proto(32,10, avx2);
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#endif // AVCODEC_X86_HEVCDSP_H
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@ -54,59 +54,17 @@ LFL_FUNCS(uint8_t, 8, ssse3)
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LFL_FUNCS(uint8_t, 10, ssse3)
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LFL_FUNCS(uint8_t, 12, ssse3)
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#if HAVE_SSE2_EXTERNAL
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void ff_hevc_idct32_dc_add_8_sse2(uint8_t *dst, int16_t *coeffs, ptrdiff_t stride)
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{
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ff_hevc_idct16_dc_add_8_sse2(dst, coeffs, stride);
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ff_hevc_idct16_dc_add_8_sse2(dst+16, coeffs, stride);
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ff_hevc_idct16_dc_add_8_sse2(dst+16*stride, coeffs, stride);
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ff_hevc_idct16_dc_add_8_sse2(dst+16*stride+16, coeffs, stride);
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}
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#define IDCT_FUNCS(W, opt) \
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void ff_hevc_idct##W##_dc_8_##opt(int16_t *coeffs); \
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void ff_hevc_idct##W##_dc_10_##opt(int16_t *coeffs)
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void ff_hevc_idct16_dc_add_10_sse2(uint8_t *dst, int16_t *coeffs, ptrdiff_t stride)
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{
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ff_hevc_idct8_dc_add_10_sse2(dst, coeffs, stride);
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ff_hevc_idct8_dc_add_10_sse2(dst+16, coeffs, stride);
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ff_hevc_idct8_dc_add_10_sse2(dst+8*stride, coeffs, stride);
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ff_hevc_idct8_dc_add_10_sse2(dst+8*stride+16, coeffs, stride);
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}
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void ff_hevc_idct32_dc_add_10_sse2(uint8_t *dst, int16_t *coeffs, ptrdiff_t stride)
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{
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ff_hevc_idct16_dc_add_10_sse2(dst, coeffs, stride);
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ff_hevc_idct16_dc_add_10_sse2(dst+32, coeffs, stride);
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ff_hevc_idct16_dc_add_10_sse2(dst+16*stride, coeffs, stride);
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ff_hevc_idct16_dc_add_10_sse2(dst+16*stride+32, coeffs, stride);
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}
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#endif //HAVE_SSE2_EXTERNAL
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#if HAVE_AVX_EXTERNAL
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void ff_hevc_idct16_dc_add_10_avx(uint8_t *dst, int16_t *coeffs, ptrdiff_t stride)
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{
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ff_hevc_idct8_dc_add_10_avx(dst, coeffs, stride);
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ff_hevc_idct8_dc_add_10_avx(dst+16, coeffs, stride);
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ff_hevc_idct8_dc_add_10_avx(dst+8*stride, coeffs, stride);
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ff_hevc_idct8_dc_add_10_avx(dst+8*stride+16, coeffs, stride);
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}
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void ff_hevc_idct32_dc_add_10_avx(uint8_t *dst, int16_t *coeffs, ptrdiff_t stride)
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{
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ff_hevc_idct16_dc_add_10_avx(dst, coeffs, stride);
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ff_hevc_idct16_dc_add_10_avx(dst+32, coeffs, stride);
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ff_hevc_idct16_dc_add_10_avx(dst+16*stride, coeffs, stride);
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ff_hevc_idct16_dc_add_10_avx(dst+16*stride+32, coeffs, stride);
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}
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#endif //HAVE_AVX_EXTERNAL
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#if HAVE_AVX2_EXTERNAL
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void ff_hevc_idct32_dc_add_10_avx2(uint8_t *dst, int16_t *coeffs, ptrdiff_t stride)
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{
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ff_hevc_idct16_dc_add_10_avx2(dst, coeffs, stride);
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ff_hevc_idct16_dc_add_10_avx2(dst+32, coeffs, stride);
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ff_hevc_idct16_dc_add_10_avx2(dst+16*stride, coeffs, stride);
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ff_hevc_idct16_dc_add_10_avx2(dst+16*stride+32, coeffs, stride);
|
||||
}
|
||||
#endif //HAVE_AVX2_EXTERNAL
|
||||
IDCT_FUNCS(4x4, mmxext);
|
||||
IDCT_FUNCS(8x8, mmxext);
|
||||
IDCT_FUNCS(8x8, sse2);
|
||||
IDCT_FUNCS(16x16, sse2);
|
||||
IDCT_FUNCS(32x32, sse2);
|
||||
IDCT_FUNCS(16x16, avx2);
|
||||
IDCT_FUNCS(32x32, avx2);
|
||||
|
||||
#define mc_rep_func(name, bitd, step, W, opt) \
|
||||
void ff_hevc_put_hevc_##name##W##_##bitd##_##opt(int16_t *_dst, ptrdiff_t dststride, \
|
||||
|
|
@ -504,8 +462,8 @@ void ff_hevcdsp_init_x86(HEVCDSPContext *c, const int bit_depth)
|
|||
|
||||
if (bit_depth == 8) {
|
||||
if (EXTERNAL_MMXEXT(mm_flags)) {
|
||||
c->transform_dc_add[0] = ff_hevc_idct4_dc_add_8_mmxext;
|
||||
c->transform_dc_add[1] = ff_hevc_idct8_dc_add_8_mmxext;
|
||||
c->idct_dc[0] = ff_hevc_idct4x4_dc_8_mmxext;
|
||||
c->idct_dc[1] = ff_hevc_idct8x8_dc_8_mmxext;
|
||||
}
|
||||
if (EXTERNAL_SSE2(mm_flags)) {
|
||||
c->hevc_v_loop_filter_chroma = ff_hevc_v_loop_filter_chroma_8_sse2;
|
||||
|
|
@ -515,8 +473,9 @@ void ff_hevcdsp_init_x86(HEVCDSPContext *c, const int bit_depth)
|
|||
c->hevc_h_loop_filter_luma = ff_hevc_h_loop_filter_luma_8_sse2;
|
||||
}
|
||||
|
||||
c->transform_dc_add[2] = ff_hevc_idct16_dc_add_8_sse2;
|
||||
c->transform_dc_add[3] = ff_hevc_idct32_dc_add_8_sse2;
|
||||
c->idct_dc[1] = ff_hevc_idct8x8_dc_8_sse2;
|
||||
c->idct_dc[2] = ff_hevc_idct16x16_dc_8_sse2;
|
||||
c->idct_dc[3] = ff_hevc_idct32x32_dc_8_sse2;
|
||||
}
|
||||
if (EXTERNAL_SSSE3(mm_flags) && ARCH_X86_64) {
|
||||
c->hevc_v_loop_filter_luma = ff_hevc_v_loop_filter_luma_8_ssse3;
|
||||
|
|
@ -535,12 +494,13 @@ void ff_hevcdsp_init_x86(HEVCDSPContext *c, const int bit_depth)
|
|||
QPEL_LINKS(c->put_hevc_qpel, 1, 1, qpel_hv, 8, sse4);
|
||||
}
|
||||
if (EXTERNAL_AVX2(mm_flags)) {
|
||||
c->transform_dc_add[3] = ff_hevc_idct32_dc_add_8_avx2;
|
||||
c->idct_dc[2] = ff_hevc_idct16x16_dc_8_avx2;
|
||||
c->idct_dc[3] = ff_hevc_idct32x32_dc_8_avx2;
|
||||
}
|
||||
} else if (bit_depth == 10) {
|
||||
if (EXTERNAL_MMXEXT(mm_flags)) {
|
||||
c->transform_dc_add[0] = ff_hevc_idct4_dc_add_10_mmxext;
|
||||
|
||||
c->idct_dc[0] = ff_hevc_idct4x4_dc_10_mmxext;
|
||||
c->idct_dc[1] = ff_hevc_idct8x8_dc_10_mmxext;
|
||||
}
|
||||
if (EXTERNAL_SSE2(mm_flags)) {
|
||||
c->hevc_v_loop_filter_chroma = ff_hevc_v_loop_filter_chroma_10_sse2;
|
||||
|
|
@ -550,9 +510,9 @@ void ff_hevcdsp_init_x86(HEVCDSPContext *c, const int bit_depth)
|
|||
c->hevc_h_loop_filter_luma = ff_hevc_h_loop_filter_luma_10_sse2;
|
||||
}
|
||||
|
||||
c->transform_dc_add[1] = ff_hevc_idct8_dc_add_10_sse2;
|
||||
c->transform_dc_add[2] = ff_hevc_idct16_dc_add_10_sse2;
|
||||
c->transform_dc_add[3] = ff_hevc_idct32_dc_add_10_sse2;
|
||||
c->idct_dc[1] = ff_hevc_idct8x8_dc_10_sse2;
|
||||
c->idct_dc[2] = ff_hevc_idct16x16_dc_10_sse2;
|
||||
c->idct_dc[3] = ff_hevc_idct32x32_dc_10_sse2;
|
||||
}
|
||||
if (EXTERNAL_SSSE3(mm_flags) && ARCH_X86_64) {
|
||||
c->hevc_v_loop_filter_luma = ff_hevc_v_loop_filter_luma_10_ssse3;
|
||||
|
|
@ -569,14 +529,9 @@ void ff_hevcdsp_init_x86(HEVCDSPContext *c, const int bit_depth)
|
|||
QPEL_LINKS(c->put_hevc_qpel, 1, 0, qpel_v, 10, sse4);
|
||||
QPEL_LINKS(c->put_hevc_qpel, 1, 1, qpel_hv, 10, sse4);
|
||||
}
|
||||
if (EXTERNAL_AVX(mm_flags)) {
|
||||
c->transform_dc_add[1] = ff_hevc_idct8_dc_add_10_avx;
|
||||
c->transform_dc_add[2] = ff_hevc_idct16_dc_add_10_avx;
|
||||
c->transform_dc_add[3] = ff_hevc_idct32_dc_add_10_avx;
|
||||
}
|
||||
if (EXTERNAL_AVX2(mm_flags)) {
|
||||
c->transform_dc_add[2] = ff_hevc_idct16_dc_add_10_avx2;
|
||||
c->transform_dc_add[3] = ff_hevc_idct32_dc_add_10_avx2;
|
||||
c->idct_dc[2] = ff_hevc_idct16x16_dc_10_avx2;
|
||||
c->idct_dc[3] = ff_hevc_idct32x32_dc_10_avx2;
|
||||
|
||||
}
|
||||
} else if (bit_depth == 12) {
|
||||
|
|
|
|||
|
|
@ -598,7 +598,9 @@
|
|||
%endmacro
|
||||
|
||||
%macro SPLATW 2-3 0
|
||||
%if mmsize == 16
|
||||
%if cpuflag(avx2) && %3 == 0
|
||||
vpbroadcastw %1, %2
|
||||
%elif mmsize == 16
|
||||
pshuflw %1, %2, (%3)*0x55
|
||||
punpcklqdq %1, %1
|
||||
%elif cpuflag(mmxext)
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user