TIS-100-FPGA/source/registerMultiplex.luc

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/**
Takes a value and many registers and writes the value to one specified register
*/
module registerMultiplex (
input clk, // clock
input rst, // reset
input selection[3], //which register? see node.luc for enumeration
output acc[GNode.WORDLEN],
output up[GNode.WORDLEN],
output right[GNode.WORDLEN],
output down[GNode.WORDLEN],
output left[GNode.WORDLEN],
input lastadr[GNode.REGISTERADDRLEN], //CAUTION! JUST AN ADDRESS!
output any[GNode.WORDLEN],
output acc_w,
output up_w,
output right_w,
output down_w,
output left_w,
output any_w,
input in[GNode.WORDLEN],
input write
) {
always {
acc_w = write && selection == 1;
up_w = write && selection == 2;
right_w = write && selection == 3;
down_w = write && selection == 4;
left_w = write && selection == 5;
any_w = write && selection == 7;
acc = selection == 1 ? in : 0;
up = selection == 2 ? in : 0;
right = selection == 3 ? in : 0;
down = selection == 4 ? in : 0;
left = selection == 5 ? in : 0;
any = selection == 7 ? in : 0;
if(write && selection == 6) {
//last register
//TODO: this
}
}
}