50 lines
1.7 KiB
Plaintext
50 lines
1.7 KiB
Plaintext
module mojo_top (
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input clk, // 50MHz clock
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input rst_n, // reset button (active low)
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output led [8], // 8 user controllable LEDs
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input cclk, // configuration clock, AVR ready when high
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output spi_miso, // AVR SPI MISO
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input spi_ss, // AVR SPI Slave Select
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input spi_mosi, // AVR SPI MOSI
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input spi_sck, // AVR SPI Clock
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output spi_channel [4], // AVR general purpose pins (used by default to select ADC channel)
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input avr_tx, // AVR TX (FPGA RX)
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output avr_rx, // AVR RX (FPGA TX)
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input avr_rx_busy // AVR RX buffer full
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) {
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sig rst; // reset signal
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sig clk2;
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sig subclk[3]; //alows for 8 subclock pulses
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.clk(clk) {
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// The reset conditioner is used to synchronize the reset signal to the FPGA
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// clock. This ensures the entire FPGA comes out of reset at the same time.
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reset_conditioner reset_cond;
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.rst(rst) {
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counter slow_clk(#SIZE(15), #DIV(15));
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}
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}
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.clk(clk2), .rst(rst), .subclk(subclk) {
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node nodeA(.up_in(GNode.NULL), .right_in(GNode.NULL), .down_in(GNode.NULL), .left_in(GNode.NULL));
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}
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always {
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reset_cond.in = ~rst_n; // input raw inverted reset signal
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rst = reset_cond.out; // conditioned reset
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clk2 = slow_clk.value[11];
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subclk = slow_clk.value[13:11];
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led = c{nodeA.left_out.in[3:0], subclk, clk2};
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// led = 8h00; // turn LEDs off
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spi_miso = bz; // not using SPI
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spi_channel = bzzzz; // not using flags
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avr_rx = bz; // not using serial port
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}
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} |